Design-Reuse

Cadence Receives Three TSMC Partner of the Year Awards for Design IP, 16nm FinFET and 3D-IC Solutions

SAN JOSE, Calif. -- October 1, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today received three TSMC Partner of the Year Awards during ...
Business Wire

Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (NASDAQ:CDNS) today announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process ...
Business Wire

Cadence Digital, Custom/Analog Design Flows Certified and Design IP Available for Intel 16 FinFET Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced its digital and custom/analog flows are certified on the Intel 16 FinFET process technology and its ...
Design-Reuse

Cadence and TSMC Strengthen Collaboration on Design Infrastructure for 16nm FinFET Process Technology

SAN JOSE, Calif -- Apr 8, 2013 -- Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced an ongoing multi-year agreement with TSMC to develop the design infrastructure for 16-nanometer FinFET ...
Digi Times

HiSilicon expands adoption of Cadence tools and IP for advanced-node FinFET designs

Cadence Design Systems announced on December 1 that HiSilicon Technologies has signed an agreement to significantly expand its use of the Cadence digital and custom/analog flows for 16nm FinFET ...
Yahoo Finance

Cadence (CDNS) Receives Certification for Intel 16 FinFET

Cadence Design Systems CDNS announced that its digital and custom/analog flows had received certification on Intel's 16 FinFET process technology. Additionally, Cadence's design intellectual property ...
Nasdaq

Cadence (CDNS) Unveils New UltraLink D2D PHY IP Solutions

Cadence Design Systems, Inc CDNS unveiled UltraLink D2D PHY (physical interfaces) IP for Taiwan Semiconductor Manufacturing Company’s TSM 7 nanometer (nm) FinFET (Fin Field Effect Transistor) process ...
Nasdaq

Cadence’s New Flow Automates Custom/Analog Design Migration on TSMC Advanced Technologies

Companies to enable easy node-to-node migration for analog blocks with enhanced PDK across multiple FinFET processes to accelerate design closure Early customers seeing more than 2.5X design cycle ...
Digi Times

Cadence digital and custom/analog tools achieve TSMC certification for 10nm FinFET early design starts

Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most-current version of 10nm FinFET Design Rule Manual (DRM) and SPICE ...
CNN

Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms

TSMC and Cadence have collaborated on an integrated flow based on tool certification targeting TSMC's 7nm mobile and HPC platforms. The integrated flow ensures that the certified tools work seamlessly ...
New Electronics

Cadence achieves EDA Certification for TSMC 5nm and 7nm+ FinFET process technologies

Cadence Design Systems has announced its continued collaboration with TSMC to certify its design solutions for TSMC 5nm and 7nm+ FinFET process technologies for mobile and high-performance computing ...